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Re: Domestic microprocessors (2) (a part 8)

vss : envy to that, Is visible only...   was  and sawyers till now on freedom.
smile
Adding from 12/10/2016 12:43:
milaro222 : the purpose to occupy the market in volume of 2.1 trillion dollars.
Well, probably the purpose not the market to occupy, and  pair-triple trillions dollars...
Interesting,  spanked  or in Russia next Ostap of Bendery was got?
"Quantum networks";
"Quantum computers";
"Elbrus";
"";
"We strike automobile race on impassability and sloppiness!";
"All in Society for the Promotion of Motoring and Road Improvement!";
"Beforehand having a snack, we continue our roundabout way!".
smile

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Re: Domestic microprocessors (2) (a part 8)

[i] Now unless not so? I will not be surprised that at sale of Elbrus there is a requirement that it was stored and exploited in a protected location with the restricted tolerance. It is almost assured that so it and is c/o/I]
If at you a paranoia, it does not mean that nobody pursues you, but generally - there are no such requirements.

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Re: Domestic microprocessors (2) (a part 8)

[off]

threeman :
vss : envy to that, Is visible only...   was  and sawyers till now on freedom.
smile

And to those who something does, envy too is visible. [/off]

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Re: Domestic microprocessors (2) (a part 8)

vss : Unless? On which errors in implementation of the architecture developed by Babayan, here it was specified, what lacks of the organization of the operations leading to errors, were considered.

  (only some points from very long list):
-Duplication of a register file which, on a local consensus, is a principal cause of restriction of frequency;
-Neglect dynamic methods of optimization (a prediction of passages, hardware  etc.);
-The aspiration to make all is independent (the list resulted earlier), despite obvious shortage of possibilities for this purpose;
-Choice [del] Vanderbildihi [/del] Intel as the sample for imitation, in the best traditions of the immortal composition of Ilfa and Petrov;
-Critical mass of the produced and outstanding promises, non-recognition of the last errors, absence of objective comparing with competitors;
-Closeness of systems of development and inaccessibility of Elbrus for independent  and access of enthusiasts;
-Absence of marketing as that, beginning from necessity of research of a potential demand for Elbruses and finishing bad circle: expensively because it is a little produced, it is a little produced because that is issued - is necessary for - nobody; it is necessary for nobody because expensively and slowly.
Well etc.

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Re: Domestic microprocessors (2) (a part 8)

VLev :
Well etc.

Here in one list both technical, and organizational aspects, last, probably, are not errors of implementation of architecture.
To argue, as it is necessary to supervise over development, it is possible long - here all can have valuable advice as it is better.
It would be desirable to be restricted to understanding of a technical aspect.

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Re: Domestic microprocessors (2) (a part 8)

vss what lacks of the organization of the operations leading to errors...
?

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Re: Domestic microprocessors (2) (a part 8)

VLev :
-Neglect dynamic methods of optimization (a prediction of passages, hardware  etc.);

So time talk came about errors into architecture implementations any hardware optimization complicates a construction and increases probability of an error, which leads to that it is necessary to reduce frequency and productivity to provide reliable functioning of the processor.
I do not understand that means, when here speak about errors by development. I assume that for the Russian organization it is difficult to provide, that the processor generally earned, it is difficult to provide control of correctness of passage of all development cycles of the designer documentation, not to pass any important trifle because of which it is necessary to alter all, and time and means for it any more will not be. The problem in that though something to make operating is in itself very difficultly. It is visible that at us very few people undertakes to develop rather productive processors completely.
It is how much easy to connect dynamic methods of optimization to optimization at a compilation stage is other question. The trivial thought which here comes to mind - that at performance of the same function by two mechanisms simultaneously can arise their interference, palpation, and they will sometimes strengthen the effect, and sometimes and to bring to naught. The in itself combination of two mechanisms demands presence of some of the third, something like the damper. It is more than miscellaneous in system - does not mean better.
It at level of the most general reasonings. It is necessary was specific to look in architecture to understand, whether dynamic optimization and if helps, where helps it.
As though it was no question to the main lines of architecture, instead of how the organization with potentially  developers implements it.
Adding from 12/11/2016 01:22:

VLev :
-Choice [del] Vanderbildihi [/del] Intel as the sample for imitation,

In this branch of Intel too the sample.
Adding from 12/11/2016 01:38:

VLev :
-Closeness of systems of development and inaccessibility of Elbrus for independent  and access of enthusiasts;

it is possible, development in such state that enthusiasts-singles do not help it. And for the organizations of closeness is not present - customers receive and test. Another matter that is such users who do system for itself, instead of for sale by all interested person. But, on the other hand, who can wish to buy Elbrus when in shops machines on  processors with  OS are generally available? What for to try for the sake of few enthusiasts who do not represent solvent demand on  on microprocessors.
Probably, it is important to fulfill the orders defining well-being of the organization.
It is possible to assume that the organization already has long enough list of hardware both program bugs, and additional independent  are not necessary yet.

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vss I do not understand that means, when here speak about errors by development.
What for generally then to start this talk?
That again all to reduce to modular programming?:lol:

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Re: Domestic microprocessors (2) (a part 8)

VLev
  (only some points from very long list):
-Duplication of a register file which, on a local consensus, is a principal cause of restriction of frequency;

Elbrus-8S2 - the further development of architecture: a failure from cluster system of a kernel and duplication of the Russian Federation and a cache of 1 level.
The partial passage on full-custom design of the Russian Federation and storage of the data and tags of a cache of 1 level with cells of storage of own development.
Now these units are capable to work on frequencies to 2,6 GHz.
http://mcst.ru/files/556f68/da0cd8/50e8 … elbrus.pdf
- Neglect dynamic methods of optimization (a prediction of passages, hardware  etc.);
Elbrus-1S + wanted to build in the predictor of passages, but did not make progress in time. Build in in  models, probably.
http://www.mcst.ru/files/5847d1/e80cd8/ … elbrus.pdf
is - hardware-software.
(facebook.1486783941) Valeriy Shunkov
My God, how many time repeated a pattern... Please, cease to duplicate this bosh about standard cells and  circuits. All  circuits become on libraries of standard numeral cells, I as practising developer ASIC responsibly declare it to you.
Let's not cease, while you do not cease to broadcast this nonsense about "All  the circuit become on libraries of standard numeral cells" .
Here to you the answer from the present developers from :

In the first of these projects cache L1 has been implemented as two two-port units in total capacity of 64 Kbytes with independent ports of reading and united for
Supports of similarity given by record ports.
However, the requirement analysis, delivered in the second project, showed that the standard memory blocks generated by industrial compilers, do not allow to receive the frequency of operation set in the project "ProtsessorYo-9" .
Circuitry decisions have been as a result offered, and custom units of storage , having four ports of reading and two ports of record (the topology is developed for storage of the data) both four ports of reading and one port of record (for storage of tags), providing necessary temporal characteristics.

and even the cell of storage for these new custom units in  has been designed from zero,  that standard cells of compilers Dolphin, Synopsys and TSMC
Appeared too slow and guzzling.

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VLev :
-Critical mass of the produced and outstanding promises,

As to whom promised? Announcements for general public are not obligations. It is an estimation of possibilities which can become the validity at selection of sufficient resources for their realization. Responsible promises are given at the technical project coordination. Under  money gives. And  are fulfilled - differently it is nothing the organization would be to exist.
Here permanently confuse the Russian organization living on performance of orders on , to firms which conduct development on own means.
Any profit on sale of computers of the Minister of Defence should be, but the norm of this profit, most likely, is restricted by governmental decrees, and it is a lot of on it will not earn. Like as under state contracts on  any part should be financed from off-budget means, at the expense of the enterprise. Here the planned rate of return, probably, also is installed in coordination with this share of off-budget financing.
But it is my assumptions. Probably, all not so. It would be desirable, that understanding economic problems here explained.

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vss
Announcements for general public are not obligations.
Certainly, they initially were lies

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Re: Domestic microprocessors (2) (a part 8)

vss It is an estimation of possibilities
And this estimation obviously was erratic (it is softly told).
However, my list at all did not pursue the aim to convince you or other opponents in an informative part of these errors.
I was specific answered your question:
> On which errors in implementation of the architecture developed by Babayan, here it was specified, what lacks of the organization of the operations leading to errors, were considered.
Everything that I enumerated - - was already repeatedly considered in this branch, and at the moment of arguing - - the facts and arguments were mentioned. So lift a branch - re-read, and on ten times to repeat same - me not especially interesting.

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VLev :
Everything that I enumerated - - was already repeatedly considered in this branch, and at the moment of arguing - - the facts and arguments were mentioned.

yes. But it is all not those errors of developers that testify about them "". And talk now arose about it. That insufficient productivity can be a consequence of errors in architecture implementation. That the version here is not considered that during implementation of the big contract design for the organization the miscalculations leading to necessity to reduce productivity that the processor generally earned were admitted. Errors at a design engineering stage.
Well and possibility of such errors is put in the technical project, because of what digit there not so beautiful as originally calculated.

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vss not those errors of developers that testify about them ""
The question about "" arose in very narrow context - - concerning Spark's frequency (at all Elbrus).
And I, by the way, in reply to it resulted the reasons that there any  was not.
But you, as usual, started to generalize - - and the list of "errors" arose in reply to this generalization.
Adding from 12/11/2016 18:29:
vss Well and possibility of such errors is put in the technical project, because of what digit there not so beautiful as originally calculated
:eyes:
In  digits just beautiful - - differently . would be received by competitors (real competitors, instead of Intel).
Only in a reality these beautiful digits  are interesting to nobody. And they were not fulfilled quite often.

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Puhich
I actually here that wanted to ask. You when you read, the impression is added that Elbrus - really digging, because let and hardly, but all feeble places are found, designated and in general are solved, and us one continuous now waits some wines.
It is difficult to expect break when for development of each new model of the processor select on 6 million $. Here difficult evolutionary development is faster.
Why then to us do not show bake?
Show, when time comes.

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milaro222 :

BlazeBlaze :
You will laugh, but expensive and difficult  appeared on MiG-31 because of impossibility to implement cheap rockets with the active induction. So peep about processors, instead of about

If it was so, all over the world already for a long time refused from expensive and difficult  and the more so , on that that with rockets with the active induction at anybody for a long time already problems are not present.

And you at all in a subject. Look how many years Americans lead up aim-120 and how many years we suffered with similar .
Because of creation 120 Americans did not become  with  on fighters, and  to which they passed, has many other pluses and bonuses, besides induction of rockets. Huge reliability and LPI a mode including. So be returned in processors, instead of to a radar and rockets in which at you even amateur knowledge is not present

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Razboynik :
Show, when time comes.

And you remember as the time sharing system in computer SM has been arranged? A batch mode remember? How it is all worked?
For a long time it is time to deliver Elbrus on a hosting-platform and  to sell machine time that each interested person could familiarize with Elbrus. Make initiating registration at least with the requirement to send the scanned copy of the passport that the nobility to whom trust access. Even on such restrictions I am ready to go to satisfy curiosity.
And the computer SM reminded from irony shares - those who at least time sat down its terminal, are not surprised to brakes. . . Anyway Elbrus is progressive (in comparison with SM). Whether pulls Elbrus at least fifty o ssh connections? Should. Anyway there should be faster, than a computer SM.
[off] Only do not forget to adjust limits.conf [/off]

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Re: Domestic microprocessors (2) (a part 8)

Razboynik
We do not cease, while you do not cease to broadcast this nonsense about "All  the circuit become on libraries of standard numeral cells".
Tell to me even more about my operation) you only confirmed with the post - not only that feeblly understand a subject, but also that did not find time to descend at all under links which I specially for you found.
Here to you the answer from the present developers from :
The present developers from  specially for you wrote: custom units of storage . Read by words: custom units . The Cache memory is typical hard IP the unit which, certainly, for any not absolutely standard applications (well there four ports of record and two ports of reading) is projected by hands and which has no relation to library elements about which we like as spoke.
Even the cell of storage for these new custom units in  has been designed from zero
, here it both is called hard IP and does not concern antagonism full-custom design and the assembly on library elements, no less than a thing of type PLL, physical levels of interfaces or any . On designing of a cell of storage manually I protected the dissertation)
Therefore once again you I ask, cease to broadcast bosh that at "Elbrus" low frequency of that they are forced to use library elements, and full custom design cannot make. I to you gave quite specific references confirming that NXP and Intels project on libraries of standard elements. In the link from Intel, by the way, explicitly it is told that the cache is the main both on the area, and on number of transistors the unit which gathers manually, but you reading links from the opponent in dispute, instead to repeat the mantras much more cheerfully and to stick opponent more grounded technically with improper citations from "the present developers ", which my words in any way do not refute.
Be simply appeased, recognize that you are wrong and listen, when to you tell about how it is actually, not  theorists, and the people really working in the industry.

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Razboynik
Show, when time comes.
When the sun turns to the red giant?:rolleyes:
Time came for a long time and already it seems transited absolutely.

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Razboynik for development of each new model of the processor select on 6 million $
On $6 million a year.
And, according to reports - - it is quite enough for several iterations of test manufacture, even on the advanced technologies.
Well and would give, say, $100 million a year - - for what them will spend ?

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VLev :
Well and would give, say, $100 million a year - - for what them will spend ?

Really, how much really to expand a field of operations on domestic microprocessors within the limits of one project? Same it is necessary to be able to coordinate operation of different groups that did not hinder each other, and did common cause. Who at us possesses appropriate abilities? Well also there should be prepared frames.
But on pair superfluous iterations money would be useful. Would accelerate operation.

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vss
Really, how much really to expand a field of operations on domestic microprocessors within the limits of one project?
Families KOMDIV32 and 64 is an answer to your question.

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(facebook.1486783941) Valeriy Shunkov :
vss
Really, how much really to expand a field of operations on domestic microprocessors within the limits of one project?
Families KOMDIV32 and 64 is an answer to your question.

I did not understand - from injection of developers of Elbruses in development Komdivov or from injection of developers Komdivov in development of Elbruses turns out something more productive, than these development now give separately?

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vss
I did not understand - from injection of developers of Elbruses in development Komdivov or from injection of developers Komdivov in development of Elbruses turns out something more productive, than these development now give separately?
Developers  successfully develop within the limits of one big project a little very different under tasks, productivity, design norms of rulers of processors. Here so - precisely really to expand.

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(facebook.1486783941) Valeriy Shunkov :
, here it both is called hard IP and does not concern antagonism full-custom design and the assembly on library elements, no less than a thing of type PLL, physical levels of interfaces or any . On designing of a cell of storage manually I protected the dissertation)

Finish already with demagogy and do not cling to terminology, under full-custom here nobody understood that all chip should be designed manually, it can be only separate units.
In article it is clearly written that used standard units generated by the compiler after designed the unit it was possible to lift frequency earlier.