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Topic: Code performance on FPGA

Felt a little SDSoC -  certainly and brakes godlessly, but the idea to compile a C ++ for execution on FPGA very much is pleasant to me. Somebody already studied this subject?... <<RSDN@Home 1.0.0 alpha 5 rev. 0>>

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Re: Code performance on FPGA

Hello, CoderMonkey, you wrote: CM> Felt a little SDSoC -  certainly and brakes godlessly, but the idea to compile a C ++ for execution on FPGA very much is pleasant to me. CM> Somebody already studied this subject? My previous company spent a heap  for this subject, including purchase of not profile company specializing on  for code transfer on FPGA. Everyone should be led changes of the source code in models through repeated labor-consuming optimization. Were played year 3 and closed. Business was about 5 years ago.

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Re: Code performance on FPGA

Hello, novitk, you wrote: N> Everyone should be led changes of the source code in models through repeated labor-consuming optimization. And how this process generally worked? Used a ready product or something the?... <<RSDN@Home 1.0.0 alpha 5 rev. 0>>

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Re: Code performance on FPGA

Hello, CoderMonkey, you wrote: CM> Felt a little SDSoC -  certainly and brakes godlessly, but the idea to compile a C ++ for execution on FPGA very much is pleasant to me. Foolish idea. It is necessary javascript to use

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Re: Code performance on FPGA

Hello, CoderMonkey, you wrote: CM> And how this process generally worked? Used a ready product or something the? Used a ready product which became the as its company letting out simply bought together with developers. The product helped, but to all-around automation there was as to the moon. To provide compatibility of models between 86 and FPGA it was very expensive (if at all really). The port of "simple" model occupied ~3-4 month. To write at once and only under FPGA to us it was impossible. If compatibility is not necessary, it is necessary to look, efficiency by due optimization of data streams there the good.

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Re: Code performance on FPGA

Hello, CoderMonkey, you wrote: CM> Felt a little SDSoC -  certainly and brakes godlessly, but the idea to compile a C ++ for execution on FPGA very much is pleasant to me. CM> Somebody already studied this subject? If you like this idea you at all there look. In it the direction is many operating time and first of all it https://ru.wikipedia.org/wiki/SystemC.

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Re: Code performance on FPGA

Hello, alex_public, you wrote: _> If you like this idea you at all there look. In it the direction is many operating time and first of all it https://ru.wikipedia.org/wiki/SystemC. It is necessary to rewrite the code. The idea "simply to recompile" it is much more interesting, if is valid though somehow works.... <<RSDN@Home 1.0.0 alpha 5 rev. 0>>

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Re: Code performance on FPGA

CM> Idea "simply to recompile" it is much more interesting, if it is valid though somehow works. It that is more interesting, but for though slightly a difficult C ++ the code the poor processor of general purpose will be compiled. And for the sake of what it is all then?

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Re: Code performance on FPGA

Hello, CoderMonkey, you wrote: _>> If you like this idea you at all there look. In it the direction is many operating time and first of all it https://ru.wikipedia.org/wiki/SystemC. CM> It is necessary to rewrite the code. The idea "simply to recompile" it is much more interesting, if is valid though somehow works. Well it looking what. I heard that some generally without any editings thrust in COTTON VELVET the whole codecs by means of SystemC. But personally I did not try this technology, so for what I will not warrant.)))