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Topic: The assembler - registers MMX - conditional branch instructions.

For the purpose of acceleration of integer 64-bit arithmetics decided to try to use an assembly insertion with usage of registers MMX (which 64-bit and as well as possible would approach for my task).
I do not know how to make a cycle with the counter or the conditional passage on equality/inequality of contents of one of MMX-registers 0.
Some complexity that the counter (kol-in cycle repetitions) at me too 64-bit.
Whether probably it to make?
Instructions JZ, JNZ I so understand, for MMX-registers not at affairs?

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Re: The assembler - registers MMX - conditional branch instructions.

Counter high orders will be constants many millions years. And what for it then?

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Re: The assembler - registers MMX - conditional branch instructions.

You consider what discharges as seniors?
Amounts of repetitions of the cycle, 33-41 bits lying in a range will be necessary to me.
All it works on a "pure" C ++ within 1 days, but it would be desirable faster, here behind it it and is necessary. smile

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Re: The assembler - registers MMX - conditional branch instructions.

MMX it is the Stone Age, 90, now is AVX - *, likely it is necessary to dig in this side. As in  them to use I do not know, but all compilers S/S ++ have an appropriate key for resolution of usage of this command set .

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Re: The assembler - registers MMX - conditional branch instructions.

Dima T wrote:

MMX it is the Stone Age, 90, now is AVX - *, likely it is necessary to dig in this side. As in  them to use I do not know, but all compilers S/S ++ have an appropriate key for resolution of usage of this command set .

Probably, probably.
But me compatibility with the different computers, some of them old enough though SSE 4 is already on all checked up is still important.
To me usage MMX is not critical, and fast 64-bit arithmetics (addition-subtraction, shifts, and-or-xor) is necessary.

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Re: The assembler - registers MMX - conditional branch instructions.

It is not necessary asm
It is enough to use intrinsics instructions.
https://software.intel.com/sites/landin … sicsGuide/

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Re: The assembler - registers MMX - conditional branch instructions.

I correctly understood, what you suggest not to write out explicitly operation with demanded registers, and to trust in the C compiler?

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Re: The assembler - registers MMX - conditional branch instructions.

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Re: The assembler - registers MMX - conditional branch instructions.

Hardly the cycle in a cycle will promote overall objective achievement (to make faster, than on a C ++ with ).

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Re: The assembler - registers MMX - conditional branch instructions.

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Re: The assembler - registers MMX - conditional branch instructions.

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Re: The assembler - registers MMX - conditional branch instructions.

The thick long register is normally compared. But I did whenever possible 32-bit counters
And in a loop body added 41-bit constants if there is such emergency. In the end
The ends the main meat of a cycle is necessary on the useful operation instead of on checks of counters.

printf ("Size of long dick = %d bytes\n", sizeof (long));
for (long dick = 6'000'000'000ul;
==> dick <6'000'000'000ul + 10;
dick ++) {
printf ("Yet another fucken long dick %llu \n", dick);
}
movabsq $6000000000, %rax
movq %rax,-8 (%rbp)
.L3:
movq-8 (%rbp), %rdx
movabsq $6000000009, %rax
==> cmpq %rax, %rdx
ja.L2
movq-8 (%rbp), %rax
movq %rax, %rsi
leaq.LC1 (%rip), %rdi
movl $0, %eax
call printf@PLT
addq $1,-8 (%rbp)
jmp.L3

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Re: The assembler - registers MMX - conditional branch instructions.

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Re: The assembler - registers MMX - conditional branch instructions.

Aha. Or hands written LLVM

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Re: The assembler - registers MMX - conditional branch instructions.

Dimitry Sibiryakov wrote:

As get out, more often hands the written assembly code turns out more slowly, than generated GCC.

While I can confirm it only. smile
Made a loop body in an assembly insertion, it turns out in 1,5 times longer. But works correctly.

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Re: The assembler - registers MMX - conditional branch instructions.

mayton wrote:

But I did whenever possible 32-bit counters and in a loop body added 41-bit constants if there is such emergency. Eventually the main meat of a cycle is necessary on the useful operation instead of on checks of counters.

The amount of possible passes of a cycle lies in a range of numbers digit capacity of 33-41 bits (it while). It would be natural to use the 64-bit register for this purpose.

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Re: The assembler - registers MMX - conditional branch instructions.

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Re: The assembler - registers MMX - conditional branch instructions.

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Re: The assembler - registers MMX - conditional branch instructions.

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Re: The assembler - registers MMX - conditional branch instructions.

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Re: The assembler - registers MMX - conditional branch instructions.

Dimitry Sibiryakov wrote:

it is passed...
Even the empty cycle of such size occupies   time. Against a pay load in its body expenditures on a cycle are normally insignificant. Not , write a cycle in With ++ with long long the counter.

We are engaged in absolutely unnecessary business. We try to finish thinking what for to it (author) the counter with 41 bit is necessary.
Purely theoretically I can assume that at it the cycle step grows or start expression is already primary
It is great.
my question on "the real task" on the former is actual.

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Re: The assembler - registers MMX - conditional branch instructions.

What for it is necessary MMX the register in x64?

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Re: The assembler - registers MMX - conditional branch instructions.

The valuable remark. I here from kind resolution of Intel made  about docks Introduction to x64 Assembly
Register RAX, RDX which participated in loop condition my test example is architecturally separated from a pack of registers FPU/MMX.
And probably there is a common sense in that that GCC collected a source code without it. At  too there are the
Cost metrics.

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Re: The assembler - registers MMX - conditional branch instructions.

Dimitry Sibiryakov wrote:

Not , write a cycle in With ++ with long long the counter.

So it is written, works.